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uart16550_latest.tar
- UART16550是较为通用的串口协议，压缩包内有4个文件可供选择，直接提供RTL源码，可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.
state_machine
- verilog编程状态机实战训练：1.本实例通过实现一个状态机来控制8个LED循环闪亮； 2. 工程在project文件夹里面； 3. 源文件和管脚分配在rtl文件夹里面； 4. 下载文件在download文件夹里面。-verilog programming state machine combat training: 1. This example by implementing a state machine to control 8 LED flashing cycle 2
ds_test12
- 在Verilog语言下用FPGA驱动DS18B20，带数码管显示，带LED报警，有报警值调整功能。这个是本人调过的，原版调通代码没改的，绝对能跑通。建议用QuatusII全编译后看一下RTL图就能理解程序是怎么工作的。-A Demo of DS18B20 on FPGA.
uart16550_VERLOG
- 采用VERILOG实现完整的UART16550协议，提供RTL代码、仿真文件-Using VERILOG achieve a complete UART16550 agreement to provide RTL code, simulation files
divider_VERILOG
- 采用VERILOG实现硬件除法器。提供RTL代码和仿真文件。-Achieved using VERILOG hardware divider. Provide RTL code and simulation files.
FFTPVerilog
- FFT Verilog RTL 经过测试与Altera FFT IP相当-FFT Verilog RTL Altera FFT IP
uart_tx
- 硬件描述语言设计的串口发送源代码UART TX SOURCE CODE-Verilog HDL UART TX RTL SOURCE CODE
NAND_flash_verilog_vhdl
- 很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。- NAND Flash Controller Reference Design =============================================================================== File List 1.
vhd2vl
- vhdl to verilog rtl converter, it support simple vhdl syntax, i think it is very useful
RTL_Compiler_synthesis.pdf
- HOW TO SYNTHESIZE VERILOG CODE USING RTL COMPILER This tutorial explains how to synthesize a verilog code using RTL Compiler. In order to do so, let’s consider the verilog codes below.
syncram
- verilog rtl and testbench code for single port sync ram
SDRAMverilog
- SDRAM verilog 串口实例 带有RTL图 及详细的注释-SDRAM verilog RTL serial examples with diagrams and detailed notes
sample_tcam.tar
- verilog RTL code for simple TCAM
01287713
- the project done in verilog for rtl
Actel_DirectCore_CORESPI_4.2.116
- Actel DirectCore CORESPI 4.2.116 Verilog and VHDL RTL source files for SPI controller on APB
ps2_soc2
- PS2 Control Verilog RTL Code
DDR2Controller
- DDR2 SDRAM Control Verilog RTL Code
des.tar
- DES Encoder and Decoder Verilog RTL Code
HDB3-encoderauncoder
- HDB3编码器与解码器，以及RTL图，使用Verilog HDL实现-HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement
sync_fifo
- 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.